A flash memory may include a memory array, which may include a large number of floating gate memory cells arranged in a plurality of memory strings. Each of the memory cells may include a floating gate field-effect transistor capable of holding a charge. The memory strings may be associated with a plurality of bit lines. Each of the bit lines may be connected to a multiplexer, e.g., a write multiplexer.
During a read operation of the flash memory, some of the bit lines may be at a selected state and some of the bit lines may be at an unselected state. A bit line to bit line capacitance and a bit line to bit line resistance between a selected bit line and an unselected bit line may affect a precharge time and/or a sensing time of the selected bit line.